ARAS: asynchronous RISC architecture simulator
نویسندگان
چکیده
In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this simulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline configuration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, the pipeline configuration can be altered to improve its performance. Thus, one can explore the design space of aynchronous pipeline architectures.
منابع مشابه
ARAS: Asynchronous RISC Architecture Simulator1
In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this sim-ulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline connguration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, t...
متن کاملPydgin for RISC-V: A Fast and Productive Instruction-Set Simulator
RISC-V is a new instruction-set architecture that encourages users to design new domain-specific extensions for their needs. This necessitates RISC-V instruction-set simulators that allow productive development, productive extension, and productive instrumentation. In addition, these simulators need to be high-performance to allow simulating real-world benchmarks. There is a productivity-perfor...
متن کاملARMSim: Simulating Advanced RISC Machine Architecture
This paper discusses the design and implementation of the ARMSim, a simulator implemented in the Java and C programming languages for the Advanced RISC Machine (ARM) processor. The intended users of this tool are those individuals interested in learning computer architecture, particularly those with an interest in the Advanced RISC Machine processor family. ARMSim facilitates the learning of co...
متن کاملWinARM - Simulating Advanced RISC Machine Architecture
This paper discusses the design and implementation of the WinARM, a simulator implemented in C for the Advanced RISC Machine (ARM) processor. The intended users of this tool are those individuals interested in learning computer architecture, particularly those with an interest in the Advanced RISC Machine processor family. WinARM facilitates the learning of computer architecture by offering a h...
متن کاملSurvey of the Counterflow Pipeline Processor Architectures
11. T H E ORIGINAL CFPP Abstract The Counterflow Pipeline Processor (CFPP) Architecture is a RISC-based pipeline processor [ l I. I t was proposed in 1994 as asynchronous processor architecture. Recently, researches have implemented it as synchronous processor architecture and later improved its design in terms of speed and performance by reducing average execution latency of instructions and m...
متن کامل